Vertical Field Effect Transistors (FETs) are suitable for high voltage applications due to their relatively high breakdown voltage, compared to FETs with shorter conduction channels. A trench superjunction power Metal Oxide Semiconductor FET (MOSFET) is a type of vertical FET typically using the reduced surface field (RESURF) effect. RESURF achieves a lower on resistance (RDSon) while still maintaining a high breakdown voltage (BVdss). In the case of an n-channel FET (NFET), RESURF is implemented in some configurations with a P doped column in an N− doped epitaxial layer grown over an N+ doped drain. In other configurations, an insulated field plate is used instead of the P doped column.
In some configurations, the N+ doped drain is an N+ substrate. Insulated field plates are arranged in trenches etched into the N− epitaxial layer grown over the drain. The N− epitaxial layer, (e.g. “epi-layer”), is also a lightly doped N− drift area of the FET, with a drain formed by the more heavily doped N+ substrate, a source formed by a heavily doped N+ region on the surface of the epi-layer, a body with a P type dopant formed for a MOSFET channel, and a gate formed between the field plate and the surface. As a result of the high-resistivity epi-layer traditionally used to support a high breakdown voltage, the on-state resistance of the FET is large. By using the RESURF effect, the drift area can be reduced substantially and/or the conductivity can be increased by using higher doping, either of which will reduce the on-state resistance without unduly compromising high breakdown voltage.
RESURF uses charge balancing to more evenly distribute the electric field strength between the source and the drain. Specifically in an NFET, the field plates are grounded to generate a negative charge distributed along the length of the plate. This distributed charge provides field termination of the positive charge in the drift area, rather than terminating the positive charge on the surface of the epi-layer at the source. Accordingly, the doping concentration of the epi-layer can be increased to lower the on-resistance.
To increase the current capacity of trench superjunction power MOSFETs, the gate area may also be increased by forming a 2-dimensional array of gates, or by forming multiple stripes of gate electrodes connected in parallel. The gate area, (also referred to as the inter-active cell area), is enclosed by a termination or isolation ring to isolate the power FET from a drain voltage and other integrated circuitry. Proper design and layout of the trench superjunction power MOSFET is important for achieving good voltage breakdown characteristics.